1. Field of the Invention
The present invention relates to a regulator integrated circuit (IC) and its application circuit, in particular, to a method of reducing the number of pins of the pulse width modulation regulator IC and a circuit thereof 2. Description of Related Art
With reference to FIG. 1 for a schematic view of a conventional synchronous buck DC-to-DC converter circuit, the DC-to-DC converter circuit includes two alternately conducted switches Q1, Q2 connected in series between an input terminal for an input voltage signal Vin and a ground terminal G. The level of an output voltage Vo can be adjusted by changing duty cycles of the two switches Q1, Q2. A filter circuit composed of an inducer L1 and a capacitor C2 is coupled to a junction of the two switches Q1, Q2 for stabilizing the output voltage Vo.
The above mentioned switches Q1, Q2 are generally N-type metal oxide semiconductor field effect transistors (MOSFETs) for the purpose of low conduction loss. However, the high voltage switch Q1 coupled to the input terminal needs a driving voltage with a potential higher than the input voltage signal Vin.
In FIG. 1, a conventional method using a bootstrap capacitor C1 to boost the level of the drive voltage so as to provide a voltage level required for driving the high voltage switch Q1 is provided. A terminal of the bootstrap capacitor C1 is coupled to a voltage supply terminal for receiving a drive voltage signal Vcc, and another terminal of the bootstrap capacitor C1 is coupled to the low voltage switch Q2. When the low voltage switch Q2 is conducted, a charging path is formed between the voltage supply terminal and the ground terminal G for charging the bootstrap capacitor C1 to raise the potential at a high voltage side of the bootstrap capacitor C1 to a level above the input voltage signal Vin in order to drive the high voltage switch Q1.
The DC-to-DC conversion circuit includes a pulse width modulation (PWM) regulator IC 11 for controlling duty cycles of the switches Q1, Q2. The PWM regulator IC 11 has eight pins, which are labeled HSD, BST, VIN, RAMP, FB, VCC, LSD and GND respectively, wherein the VIN pin is provided for receiving the input voltage signal Vin, and the GND pin is a grounded terminal, the HSD pin and the LSD pin are provided for outputting a first drive signal (HSD) and a second drive signal (LSD) for driving the high voltage switch Q1 and the low voltage switch Q2 respectively, the BST pin is provided for receiving a boost voltage for driving the high voltage switch Q1, the RAMP pin is provided for receiving a sawtooth wave signal Vramp, the VCC pin is provided for supplying a drive voltage required for the PWM regulator IC 11, and the FB pin is provided for receiving a feedback signal Vfb from an output terminal of the synchronous buck DC-to-DC converter circuit 10.
The DC-to-DC conversion circuit 10 also includes a voltage divider circuit composed of resistors R1, R2 and a feedback circuit composed of a resistor R4, a capacitor C3, a resistor R3 and a Zener diode U3. The output voltage Vo is converted into the feedback signal Vfb through the voltage divider circuit and the feedback circuit.
The bootstrap capacitor C1 is provided for generating a boost voltage with a potential higher than the input terminal signal. The RAMP pin of the PWM regulator IC 11 is coupled to a capacitor C4, which is charged and discharged alternately to generate a sawtooth wave signal Vramp for the PWM regulator IC 11 to proceed a certain comparison step, which allows the PWM controller to generate the first and second drive signals HSD, LSD to adjust the duty cycles of the transistor switches Q1, Q2.
The PWM regulator IC 11 generally contains an error amplifier installed therein for comparing the feedback signal Vfb with a reference voltage to compensate and modulate the circuit. It is necessary to connect an output terminal of the error amplifier to a capacitor (not shown in the figure) for filtering out unwanted noises contained in the feedback signal Vfb. As the capacitor is installed outside the PWM regulator IC 11, and a COMP pin (not shown in the figure) is demanded for connecting the capacitor to the PWM regulator IC 11. However, such circuit layout increases the number of pins, incurs a higher manufacturing cost, and even results in a failure of packaging the PWM regulator IC 11 into the existing standard IC packaging structure. Conversely, if the capacitor is installed inside the PWM regulator IC 11, the size of the IC would be increased, and the capacitor installed in the IC 11 cannot be adjusted according to application requirements, which may affect the flexibility of the PWM regulator IC 11 in practical applications.